? semiconductor components industries, llc, 2002 april, 2002 rev. 4 1 publication order number: mc10e137/d mc10e137, mc100e137 5vecl 8bit ripple counter the mc10e/100e137 is a very high speed binary ripple counter. the two least significant bits were designed with very fast edge rates while the more significant bits maintain standard eclinps output edge rates. this allows the counter to operate at very high frequencies while maintaining a moderate power dissipation level. the device is ideally suited for multiple frequency clock generation as well as a counter in a high performance ate time measurement board. both asynchronous and synchronous enables are available to maximize the device's flexibility for various applications. the asynchronous enable input, a_start, when asserted enables the counter while overriding any synchronous enable signals. the e137 features xored enable inputs, en1 and en2, which are synchronous to the clk input. when only one synchronous enable is asserted the counter becomes disabled on the next clk transition; all outputs remain in the previous state poised for the other synchronous enable or a_start to be asserted to re-enable the counter. asserting both synchronous enables causes the counter to become enabled on the next transition of the clk. if en1 (or en2) and clk edges are coincident, sufficient delay has been inserted in the clk path (to compensate for the xor gate delay and the internal d-flip flop setup time) to insure that the synchronous enable signal is clocked correctly, hence, the counter is disabled. all input pins left open will be pulled low via an input pulldown resistor. therefore, do not leave the differential clk inputs open. doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device. the asynchronous master reset resets the counter to an all zero state upon assertion. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the 100 series contains temperature compensation. ? differential clock input and data output pins ? v bb output for single-ended use ? synchronous and asynchronous enable pins ? asynchronous master reset ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? esd protection: > 2 kv hbm, > 100 v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 330 devices device package shipping ordering information mc10e137fn plcc28 37 units/rail mc10e137fnr2 plcc28 500 units/reel mc100e137fn plcc28 37 units/rail mc100e137fnr2 plcc28 500 units/reel marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc10e137fn awlyyww mc100e137fn awlyyww http://onsemi.com 128 128
mc10e137, mc100e137 http://onsemi.com 2 v cco 1 q0 q7 q7 q6 q6 q5 q5 q4 q4 v cc q3 q3 q2 q2 v cco q1 q1 q0 v cco mr v bb clk clk v ee en2 en1 a_start 4 3 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 8 6 5 pinout: 28-lead plcc (top view) * all v cc and v cco pins are tied together on the die. clk clk logic diagram q q clk clk d r q q clk clk d r en1 en2 clk clk a_start q q d r q0 q0 q1 q1 q q clk clk d r q7 q7 mr v bb logic diagram and pinout assignment clk, clk q0-q7, q0-q7 a_start en1, en2 mr v bb v cc , v cco v ee ecl differential clock inputs ecl differential q outputs ecl asynchronous enable input ecl synchronous enable inputs asynchronous master reset reference voltage output positive supply negative supply pin function pin description warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. sequential truth table function en1 en2 a_start mr clk q7 q6 q5 q4 q3 q2 q1 q0 reset x x x h x l l l l l l l l count l l l l l l l l l l l l z z z l l l l l l l l l l l l l l l l l l l h h h l h stop h h l l l l l l z z l l l l l l l l l l l l h h h h asynch start h h l l l l h h h l l l z z z l l l l l l l l l l l l l l l h h h l l h l h l count l l l l l l l l l l l l z z z l l l l l l l l l l l l l h h h l l h l l h l h stop l l h h l l l l z z l l l l l l l l h h l l l l h h synch start h h h h h h l l l l l l z z z l l l l l l l l l l l l h h h l l h h h l l h l stop h h l l l l l l z z l l l l l l l l h h h h l l l l count l l l l l l l l l l l l z z z l l l l l l l l l l l l h h h h h h l h h h l h reset x x x h x l l l l l l l l z = low to high transition
mc10e137, mc100e137 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee 0 v v cc = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. 10e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 121 145 121 145 121 145 ma v oh output high voltage (note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mv v ih input high voltage (single ended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage (single ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv v bb output voltage reference 3.62 3.73 3.65 3.75 3.69 3.81 v v ihcmr input high voltage common mode range (differential) (note 3) 2.2 4.6 2.2 4.6 2.2 4.6 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . 10e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 121 145 121 145 121 145 ma v oh output high voltage (note 2) 1020 930 840 980 895 810 910 815 720 mv v ol output low voltage (note 2) 1950 1790 1630 1950 1790 1630 1950 1773 1595 mv v ih input high voltage (single ended) 1170 1005 840 1130 970 810 1060 890 720 mv v il input low voltage (single ended) 1950 1715 1480 1950 1715 1480 1950 1698 1445 mv v bb output voltage reference 1.38 1.27 1.35 1.25 1.31 1.19 v v ihcmr input high voltage common mode range (differential) (note 3) 2.8 0.4 2.8 0.4 2.8 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc10e137, mc100e137 http://onsemi.com 4 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 121 145 121 145 139 167 ma v oh output high voltage (note 2) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 2) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mv v ih input high voltage (single ended) 3835 4050 4120 3835 4120 4120 3835 4120 4120 mv v il input low voltage (single ended) 3190 3300 3525 3190 3525 3525 3190 3525 3525 mv v bb output voltage reference 3.62 3.73 3.62 3.74 3.62 3.74 v v ihcmr input high voltage common mode range (differential) (note 3) 2.2 4.6 2.2 4.6 2.2 4.6 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 121 145 121 145 139 167 ma v oh output high voltage (note 2) 1025 950 880 1025 950 880 1025 950 880 mv v ol output low voltage (note 2) 1810 1705 1620 1810 1745 1620 1810 1740 1620 mv v ih input high voltage (single ended) 1165 950 880 1165 880 880 1165 880 880 mv v il input low voltage (single ended) 1810 1700 1475 1810 1475 1475 1810 1475 1475 mv v bb output voltage reference 1.38 1.27 1.38 1.26 1.38 1.26 v v ihcmr input high voltage common mode range (differential) (note 3) 3.8 0.4 3.8 0.4 3.8 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc10e137, mc100e137 http://onsemi.com 5 ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f count maximum count frequency 1800 2200 1800 2200 1800 2200 mhz t plh t phl propagation delay to output clk to q0 clk to q1 clk to q2 clk to q3 clk to q4 clk to q5 clk to q6 clk to q7 a_start to q0 mr to q0 1300 1600 1950 2275 2625 2950 3250 3575 950 700 1700 2025 2425 2750 3125 3450 3775 4075 1325 1000 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 1300 1600 1950 2275 2625 2950 3250 3575 950 700 1700 2050 2450 2775 3150 3475 3800 4125 1325 1000 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 1350 1650 2025 2350 2700 3050 3375 3700 950 700 1750 2100 2500 2850 3225 3550 3925 4250 1325 1000 2200 2550 3000 3425 3825 4250 4600 4950 1700 1300 ps t s setup time (en1, en2) 0 150 0 150 0 150 ps t h hold time (en1, en2) 300 150 300 150 300 150 ps t rr reset recovery time mr, a_start 400 200 400 200 400 200 ps t pw minimum pulse width clk, mr, a_start 400 400 400 ps v pp minimum input swing (clk) (note 1.) 0.25 1.0 0.25 1.0 0.25 1.0 v t jitter cycletocycle jitter tbd tbd tbd ps t r t f rise/fall times (20%80%) q0,q1 q2 to q7 150 275 400 600 150 275 400 600 150 275 400 600 ps 1. 10 series: v ee can vary +0.46 v / 0.06 v. 100 series: v ee can vary +0.46 v / 0.8 v. 1. minimum input swing for which ac parameters are guaranteed. full dc ecl output swings will be generated with only 50 mv input swings. figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = v cc 2.0 v
mc10e137, mc100e137 http://onsemi.com 6 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e137, mc100e137 http://onsemi.com 7 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e n m l v w d d y brk 28 1 view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t t b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view dd s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 --- 1.02 ---
mc10e137, mc100e137 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10e137/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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